Read-only-memories (ROMs) are memories into which information is permanently stored during fabrication. Such memories are considered "non-volatile" as only read operations can be performed.
Each bit of information in a ROM is stored by the presence or absence of a data path from the word (access) line to a bit (sense) line. The data path is eliminated simply by insuring no circuit element joins a word and bit line. Thus, when the word line of a ROM is activated, the presence of a signal on the bit line will mean that a 1 is stored, whereas the absence of a signal indicates that a 0 is stored.
If only a small number of ROM circuits are needed for a specific application, custom mask fabrication might be too expensive or time consuming. In such cases, it would be faster and cheaper for users to program each ROM chip individually. ROMs with such capabilities are referred to as programmable read-only-memories (PROMs). In the first PROMs which were developed, information could only be programmed once into the construction and then could not be erased. In such PROMs, a data path exists between every word and bit line at the completion of the chip manufacture. This corresponds to a stored 1 in every data position. Storage cells during fabrication were selectively altered to store a 0 following manufacture by electrically severing the word-to-bit connection paths. Since the write operation was destructive, once the 0 had been programmed into a bit location it could not be erased back to a 1. PROMs were initially implemented in bipolar technology, although MOS PROMs became available.
Later work with PROMs led to development of erasable PROMs. Erasable PROMs depend on the long-term retention of electric charge as the means for information storage. Such charge is stored on a MOS device referred to as a floating polysilicon gate. Such a construction differs slightly from a conventional MOS transistor gate. The conventional MOS transistor gate of a memory cell employs a continuous polysilicon word line connected among several MOS transistors which functions as the respective transistor gates. The floating polysilicon gate of an erasable PROM interposes a localized secondary polysilicon gate in between the continuous word line and silicon substrate into which the active areas of the MOS transistors are formed. The floating gate is localized in that the floating gates for respective MOS transistors are electrically isolated from the floating gates of other MOS transistors.
Various mechanisms have been implemented to transfer and remove charge from a floating gate. One type of erasable programmable memory is the so-called electrically programmable ROM (EPROM). The charge-transfer mechanism occurs by the injection of electrons into the floating polysilicon gate of selected transistors. If a sufficiently high reverse-bias voltage is applied to the transistor drain being programmed, the drain-substrate "pn" junction will experience "avalanche" breakdown, causing hot electrons to be generated. Some of these will have enough energy to pass over the insulating oxide material surrounding each floating gate and thereby charge the floating gate. These EPROM devices are thus called floating-gate, avalanche-injection MOS transistors (FAMOS). Once these electrons are transferred to the floating gate, they are trapped there. The potential-barrier at the oxide-silicon interface of the gate is greater than 3 eV, making the rate of spontaneous emission of the electrons from the oxide over the barrier negligibly small. Accordingly, the electronic charge stored on the floating gate can be retained for many years.
When the floating gate is charged with a sufficient number of electrons, inversion of the channel under the gate occurs. A continuously conducting channel is thereby formed between the source and drain exactly as if an external gate voltage had been applied. The presence of a 1 or 0 in each bit location is therefore determined by the presence or absence of a conducting floating channel gate in each program device.
Such a construction also enables means for removing the stored electrons from the floating gate, thereby making the PROM erasable. This is accomplished by flood exposure of the EPROM with strong ultraviolet light for approximately 20 minutes. The ultraviolet light creates electron-hole pairs in the silicon dioxide, providing a discharge path for the charge (electrons) from the floating gates.
In some applications, it is desirable to erase the contents of a ROM electrically, rather than to use an ultraviolet light source. In other circumstances, it would be desirable to be able to change one bit at a time, without having to erase the entire integrated circuit. Such led to the development of electrically erasable PROMs (EEPROMs). Such technologies include MNOS transistors, floating-gate tunnel oxide MOS transistors (FLOTOX), textured high-polysilicon floating-gate MOS transistors, and flash EEPROMs. Such technologies can include a combination of floating gate transistor memory cells within an array of such cells, and a peripheral area to the array which comprises CMOS transistors.
With floating gate transistors, the floating gate polysilicon (commonly referred to as Poly 1) is positioned in between the overlying word line polysilicon (commonly referred to as Poly 2) and underlying substrate. Two edges of the floating gate poly are lined up directly relative to the word line edge. This factor would make the photo and etch process very difficult if one were to try to completely define the floating gate poly first, and then pattern the word line. This would be due to the problems of photomask misalignment and photo-edge etch effect.
One approach of avoiding the problem is to first define only two edges (instead of all four edges) of the floating gate. The typical two edges patterned first are the Poly 1 floating gate edges which do not coincide with the word line edges. With this completed, a stack poly etch for the word lines during the Poly 2 etch (word line) patterning defines the word line edges as well as the remaining two edges of the floating gate. This approach is not sensitive to any misalignment due to the fact that the word line and corresponding floating gate edges "self-align" relative to each other during the same etching process.
Prior art techniques of processing erasable PROMs are described with reference to FIGS. 1A-5. FIG. 1A is a top view of a wafer fragment at one processing step, with FIG. 1B being an enlarged cross section taken through line 1B--1B of FIG. 1 during the same step. In each of the figures which follow, the "A" figure represents a top view, while the "B" view represents an enlarged cross sectional view at the same step in the described process. FIGS. 1A and 1B illustrate a wafer fragment 10 which will be defined by a memory array area 12 and an area 14 peripheral to array area 12. Wafer fragment 10 is comprised of a bulk substrate 16, which in the described embodiment is p-type, with peripheral area 14 being provided with n-well 18 for formation of CMOS transistors in the peripheral area 14 and p-well 9 in the peripheral and array area. Field oxide regions 20 and a gate insulating layer 22 are provided atop substrate 16. A first layer 24 of polysilicon (Poly 1) is applied atop insulating layers 20 and 22. A tri-layer 26 of dielectric is applied atop first polysilicon layer 24 for use in floating gate transistors to be formed within array area 12. Tri-layer 26 typically comprises an O-N-O sandwich construction.
Referring to FIGS. 2A and 2B, dielectric layer 26 and polysilicon layer 24 are etched away from peripheral area 14, and etched within array 12 to define lines 28. Lines 28 are defined by opposing edges 30a and 30b which will form the first two edges of the floating gate transistors within array 12, as will be apparent from the continuing discussion.
Referring to FIGS. 3A and 3B, a second polysilicon layer 32 is applied atop the wafer to cover peripheral area 14 and array area 12. As well, a thin higher conductive layer 34, such as WSi.sub.x, is applied atop poly layer 32. Collectively, layers 32 and 34 are considered as the Poly 2 layer.
Referring to FIGS. 4A and 4B, a layer of photoresist (not shown) is applied and patterned as illustrated to define FAMOS transistor gates 36, 38 within array area 12, and coincident word lines 29 as shown. It is necessary that peripheral area 14 be masked with photoresist during such etch to prevent trenching into the wells of substrate 16.
Referring to FIG. 5, prior art processes next pattern peripheral area 14 to form each of the word line transistor gates 35, 37, 39 and 41 in the same step. (Word lines 35, 37, 39 and 41 are not shown in the "A" figures.) Thereafter, separate photoresist masks must be applied and patterned to enable implanting of the various p and n type dopant materials required adjacent illustrated transistor gates 36, 38, 35, 37, 39 and 41. Spacers as well are formed to produce the configuration shown in FIG. 6. The prior art process from FIG. 5 to produce the construction of FIG. 6 proceeds as follows.
Photoresist is applied and patterned to mask the n-well. A punch-through boron (p-type material) implant is then conducted (typical dose of 5.times.10.sup.12 atoms/cm.sup.2) into each of the unmasked n-channel transistor regions of the array and peripheral area. A conformal layer of oxide, such as TEOS, of approximately 1000 Angstroms thickness is applied atop the wafer. Photoresist is then again applied and patterned to mask the n-well. Phosphorus (n-type material) is then implanted (typical dose of 5.times.10.sup.13 atoms/cm.sup.2) to form LDD regions 11. The photoresist is then removed, and oxide layer is applied and anisotropically etched to form spacers 13. Photoresist is then reapplied and patterned to mask the n-well. Arsenic (n-type material) is then implanted (typical dose of 5.times.10.sup.15 atoms/cm.sup.2) to form n+ source and drain regions 15. The photoresist is then removed, and then reapplied and patterned to mask everything but the n-well. Boron (p-type material) is then implanted (typical dose of 5.times.10.sup.15 atoms/cm.sup.2) to form source and drain p+ regions 17, and then the photo resist removed.
Such results in high process complexity and numerous photomasks which increase the cost and time to process the wafers. For example from FIG. 3, six photomasks are required by the above process to effect all the desired implants. At least one more photomask would be required were it desirable to optimize or modify the n-channel implants of the array transistors differently from the peripheral n-channel transistors. It would be desirable to improve upon this prior art method.
Further, the above process typically begins with the creation of N-wells and P-wells in a silicon substrate. FIGS. 7-15 illustrate the conventional N-well and P-well formation process.
Referring to FIG. 7, a pad oxide layer 111 is thermally grown on a lightly-doped P-type silicon wafer substrate 112.
Referring to FIG. 8, a silicon nitride layer 113 is deposited on top of pad oxide layer 111.
Referring to FIG. 9, future P-well regions on the substrate are masked with a photoresist layer 114.
Referring to FIG. 10, the wafer is subjected to a nitride etch, which removes those portions of silicon nitride layer 113 that are not subjacent photoresist layer 114. These regions where the nitride is removed correspond to the future N-well regions. A phosphorus implant then creates N-well regions 115, with only one such region being shown in FIG. 10.
Referring to FIG. 11, following a photoresist strip, a silicon oxide masking layer 116 is grown in the N-well regions 115 during a steam oxidization step. It will be noted that the steam well oxidation recesses only the N-well regions 115. The pattern of recessed N-well regions on the wafer is commonly used for the alignment of subsequent photomasks. During the steam oxidization step, the phosphorus atoms in the N-well regions 115 diffuse somewhat deeper into the substrate 112 and under the uplifted edges of nitride layer 113.
Referring to FIG. 12, the wafer is subjected to a boron implant which creates P-well regions 117, with only one such region being shown in FIG. 12. The silicon oxide masking layer 116 prevents the penetration of boron atoms into the N-well regions 115. It will be noted that both the phosphorus implant depicted in FIG. 10 and the boron implant depicted in FIG. 12 were made through pad oxide layer 11. Implanting through an oxide layer tends to partially deflect implanted atoms, and thus eliminates the channeling tendency that occurs when an implant is made directly into a monocrystalline silicon layer. Channeling is the propensity of a high-energy particle to travel through a silicon crystal lattice if it enters the lattice such that it travels between layers of regularly oriented silicon atoms. Small particles, such as boron atoms, are more prone to channeling than larger articles. Because of the more diverse arrangement of molecules in a silicon oxide layer, the layer will tend to deflect implanted particles in a random manner, thus allowing only a small percentage of the particles to engage in channeling.
Referring to FIG. 13, pad oxide layer 111 and masking oxide layer 116 have been removed with a first oxide etch, and a high-temperature drive step has caused the phosphorus atoms in N-well region 115 and the boron atoms in P-well region 117 to diffuse, thereby increasing the depth of each region. During the drive step, a thermal oxide layer 118 is typically grown on top of the N-well region 115 and the P-well region 117.
Referring now to FIG. 14, a second oxide etch has removed thermal oxide layer 118.
Referring to FIG. 15, a pad oxide layer 119 has been grown on both N-well regions 115 and P-wells regions 117. Additional processing is then conducted to complete the desired circuitry.
The process described immediately above is extensively used in the semiconductor industry for creating N and P-wells. The process does have a drawback in the high number of process steps involved.
Aspects of the following disclosed and claimed invention are related to our issued U.S. Pat. No. 5,175,120.